1. Technical Field
The present invention relates in general to a system and method for regulating dynamic IR (voltage) drop in an integrated circuit contained on a semiconductor substrate. In particular, the present invention relates to a system and method for regulating dynamic IR (voltage) drop in an integrated circuit in response to power required for the execution of the instructions by the integrated circuit.
2. Description of the Related Art
The power distribution network or power grid implemented for a central processing unit (CPU) core on an integrated circuit semiconductor substrate is normally designed to supply average current assuming that the switching activity occurs in a more or less uniform fashion in any given cycle, i.e., the number of circuit nodes switching at any given time interval is relatively constant.
However, in reality, the number of CPU switching circuit nodes depends upon the type of instruction being executed, the data being used by that instruction and the previous state of the nodes in the CPU circuit. The result is that a varying number of circuit nodes are switched from cycle to cycle when comparing one time interval to another. If the amount of switching requires a current less than the average current, instruction execution will proceed normally. Yet there are other times when the amount of instantaneous current or peak current required for switching is more than the average current that can be supplied by the power distribution network. This results in a demand for charge that exceeds its supply. A larger demand for charge due to a current flow whose magnitude is greater than the average current results in the collapsing of voltage across the power supply distribution network or power grid.
During these times the voltage difference between the supply voltage Vdd and the ground potential provided to the CPU integrated circuit decreases resulting in a reduction of the effective voltage provided to the transistor devices. In such a situation, the transistor performance degrades resulting in increased switching delay of the transistors which, in turn, results in an overall loss of performance.
A traditional solution to this problem is to add decoupling capacitors in the CPU integrated circuit. For clock cycles where the switching activity requires less current than is provided by the power supply, the decoupling capacitors collect charge and store it. Later, during clock cycles where the switching activity is greater and additional current is required, the decoupling capacitors provide the charge back to the CPU integrated circuit in the form of current to compensate for the difference between average current supplied to the circuit by the power distribution network and the actual peak current required for execution of instructions.
However, there are disadvantages to this solution. First, since the charging and discharging time constants for these decoupling capacitors must be small enough to charge and discharge in a fraction of a clock cycle, these decoupling capacitors require optimal sizing and layout area on the semiconductor substrate that increase manufacturing cost and decrease yield. Second, decoupling capacitors leak and additional power must be provided to compensate for this leakage.
Therefore, there is a need to compensate for peak variations due to instruction execution in the CPU without adding additional components to the CPU integrated circuit semiconductor substrate.